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Commit 57d894e7 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'renesas-clk-for-v6.2-tag1' of...

Merge tag 'renesas-clk-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Round SD clock rate to improve parent clock selection
 - Add Ethernet Switch and internal SASYNCPER clocks on R-Car S4-8
 - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
   serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI (RPC-IF)
   clocks on R-Car V4H
 - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
   RZ/G2L
 - Fix endless loop on RZ/N1
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits)
  clk: renesas: r9a06g032: Repair grave increment error
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
  clk: renesas: r8a779a0: Fix SD0H clock name
  clk: renesas: r8a779g0: Add RPC-IF clock
  clk: renesas: r8a779g0: Add SDHI clocks
  clk: renesas: r8a779f0: Add SASYNCPER internal clock
  clk: renesas: r8a779f0: Fix SD0H clock name
  clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
  clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
  clk: renesas: r8a779g0: Add TPU clock
  clk: renesas: r8a779g0: Add PWM clock
  clk: renesas: r8a779g0: Add SCIF clocks
  clk: renesas: r8a779g0: Fix HSCIF parent clocks
  clk: renesas: r8a779g0: Add SASYNCPER clocks
  clk: renesas: r9a07g044: Add MTU3a clock and reset entry
  clk: renesas: r8a779g0: Add INTC-EX clock
  clk: renesas: r8a779g0: Add MSIOF clocks
  clk: renesas: r8a779g0: Add SYS-DMAC clocks
  clk: renesas: r8a779f0: Add Ethernet Switch clocks
  ...
parents 9abf2313 02693e11
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