RISC-V: Add DT documentation for SiFive L2 Cache Controller (5545b6d1) · Commits · Mirrors / github.com / raspberrypi_linux

Unverified Commit 5545b6d1 authored May 06, 2019 by

Yash Shah Committed by Palmer Dabbelt May 16, 2019

RISC-V: Add DT documentation for SiFive L2 Cache Controller



Add device tree bindings for SiFive FU540 L2 cache controller driver

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 4c3aeb82

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