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Commit 3c220bf4 authored by Michal Simek's avatar Michal Simek
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arm: zynq: Label whole PL part as fpga_full region 



This will simplify dt overlay structure for the whole PL.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent e5e6f687
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