perf vendor events: Update events for Neoverse E1

These CPUs contain the same PMU events (as per the Arm Technical
Reference manuals for Cortex A65 and Neoverse E1)

This de-duplicates event data, and avoids issues in previous E1 event
data (not present in A65 data)
* Missing implementation defined events
* Inclusion of events that are not implemented:
  - L1D_CACHE_ALLOCATE
  - SAMPLE_POP
  - SAMPLE_FEED
  - SAMPLE_FILTRATE
  - SAMPLE_COLLISION

Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Nick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220907154932.60808-1-nick.forrington@arm.com


Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>