mmc: tegra: Write xfer_mode, CMD regs in together
If there is a gap between xfer mode and command register writes, tegra SDMMC controller can sometimes issue a spurious command before the CMD register is written. To avoid this, these two registers need to be written together in a single write operation. This is implemented as an NVQUIRK as it applies to T114, T124 and T132. Signed-off-by:Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
parent
0501be64
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