riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format

Change the timer layout in the dtb to fit the format that needed by
the SBI.

Fixes: 967a94a9

 ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>