ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0d ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by:Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@foss.st.com>
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