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Commit 18703923 authored by Rohit Khaire's avatar Rohit Khaire Committed by Alex Deucher
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drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid 



RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: default avatarRohit Khaire <rohit.khaire@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 810085dd
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