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Commit 0ff5a481 authored by Dinh Nguyen's avatar Dinh Nguyen
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ARM: dts: socfpga: fix register entry for timer3 on Arria10



Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 9123e3a7
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