- Dec 16, 2020
-
-
Bjorn Helgaas authored
- Add PCI endpoint subsystem references to MAINTAINERS (Gustavo Pimentel) * remotes/lorenzo/pci/misc: MAINTAINERS: Add missing documentation references to PCI Endpoint Subsystem
-
Bjorn Helgaas authored
- Offset client VMD MSI-X vectors (Jon Derrick) * remotes/lorenzo/pci/vmd: PCI: vmd: Offset Client VMD MSI-X vectors
-
Bjorn Helgaas authored
- Convert DT bindings to json-schema (Yoshihiro Shimoda) - Document r8a77965 DT bindings (Yoshihiro Shimoda) - Document r8a774e1 DT bindings (Lad Prabhakar) * remotes/lorenzo/pci/rcar: dt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings dt-bindings: PCI: rcar-pci-host: Document r8a77965 bindings dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema PCI: rcar: Drop unused members from struct rcar_pcie_host
-
Bjorn Helgaas authored
- Enable keystone compile testing on non-ARM arches (Alex Dewar) * remotes/lorenzo/pci/keystone: PCI: keystone: Enable compile-testing on !ARM
-
Bjorn Helgaas authored
- Declare iproc register set sizes to help avoid out-of-bound accesses (Bharat Gooty) - Invalidate iproc PAXB IARR1/IMAP1 inbound windows to erase bootloader footprint (Roman Bacik) - Log Root Port link speed & width at startup (Srinath Mannam) * remotes/lorenzo/pci/iproc: PCI: iproc: Enhance PCIe Link information display PCI: iproc: Invalidate correct PAXB inbound windows PCI: iproc: Fix out-of-bound array accesses
-
Bjorn Helgaas authored
- Support multiple ATU memory regions (Rob Herring) - Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar) - Allow programming ATU for >4GB memory (Vidya Sagar) - Move ATU offset out of driver match data (Rob Herring) - Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob Herring) - Remove unneeded function wrappers (Rob Herring) - Ensure all outbound ATU windows are reset to reduce dependencies on bootloader (Rob Herring) - Use the default MSI irq_chip for dra7xx (Rob Herring) - Drop the .set_num_vectors() host op (Rob Herring) - Move MSI interrupt setup into DWC common code (Rob Herring) - Rework and simplify DWC MSI initialization (Rob Herring) - Move link handling to DWC common code (Rob Herring) - Move dw_pcie_msi_init() calls to DWC common code (Rob Herring) - Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring) - Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring) - Revert "keystone: Drop duplicated 'num-viewport'" to prepare for detecting number of iATU regions without help from DT (Rob Herring) - Move inbound and outbound windows to common struct (Rob Herring) - Detect number of DWC iATU windows from device registers (Rob Herring) - Drop samsung,exynos5440-pcie binding (Marek Szyprowski) - Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for Exynos5433 variant (Marek Szyprowski) - Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon Chung) - Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung) - Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar) - Read tegra dbi" base address in application logic (Vidya Sagar) - Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar) - Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar) - Continue tegra unconfig sequence even if parts fail (Vidya Sagar) - Check return value of tegra_pcie_init_controller() (Vidya Sagar) - Disable tegra LTSSM during L2 entry (Vidya Sagar) - Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam) - Add SM8250 BDF to SID mapping (Manivannan Sadhasivam) - Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar) * remotes/lorenzo/pci/dwc: PCI: dwc: Set 32-bit DMA mask for MSI target address allocation PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 PCI: qcom: Add SM8250 SoC support dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC PCI: tegra: Disable LTSSM during L2 entry PCI: tegra: Check return value of tegra_pcie_init_controller() PCI: tegra: Continue unconfig sequence even if parts fail PCI: tegra: Set DesignWare IP version PCI: tegra: Fix ASPM-L1SS advertisement disable code PCI: tegra: Read "dbi" base address to program in application logic PCI: tegra: Move "dbi" accesses to post common DWC initialization PCI: dwc: exynos: Rework the driver to support Exynos5433 variant phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding PCI: dwc: Detect number of iATU windows PCI: dwc: Move inbound and outbound windows to common struct Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'" PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init() PCI: dwc: Move dw_pcie_setup_rc() to DWC common code PCI: dwc: Move dw_pcie_msi_init() into core PCI: dwc: Move link handling into common code PCI: dwc: Rework MSI initialization PCI: dwc: Move MSI interrupt setup into DWC common code PCI: dwc: Drop the .set_num_vectors() host op PCI: dwc/dra7xx: Use the common MSI irq_chip PCI: dwc: Ensure all outbound ATU windows are reset PCI: dwc/intel-gw: Remove some unneeded function wrappers PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code PCI: dwc/intel-gw: Move ATU offset out of driver match data PCI: dwc: Add support to program ATU for >4GB memory PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit PCI: dwc: Support multiple ATU memory regions
-
Bjorn Helgaas authored
- Make "cdns,max-outbound-regions" optional (Kishon Vijay Abraham I) - Fix "ti,syscon-pcie-ctrl" DT property to take argument (Kishon Vijay Abraham I) - Add TI J7200 host and endpoint mode DT bindings (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
-
Bjorn Helgaas authored
- Initialize "tmp" before use (Jim Quinlan) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: Initialize "tmp" before use
-
Bjorn Helgaas authored
- Update comment about delay before link training (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Update comment about disabling link training
-
Bjorn Helgaas authored
- Unify ECAM constants in native PCI Express drivers (Krzysztof Wilczyński) - Add thunder-pem constant for custom ".bus_shift" initialiser (Krzysztof Wilczyński) - Convert iproc to use new ECAM constants (Krzysztof Wilczyński) - Change vmd __iomem pointers from "char *" to "void *" (Krzysztof Wilczyński) - Remove unused xgene .bus_shift initialisers (Krzysztof Wilczyński) * pci/ecam: PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c PCI: vmd: Update type of the __iomem pointers PCI: iproc: Convert to use the new ECAM constants PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser PCI: Unify ECAM constants in native PCI Express drivers
-
Bjorn Helgaas authored
- Mark AMD Raven iGPU ATS as broken in some Emerson platforms to avoid issues (Alex Deucher) - Add function 1 DMA alias quirk for Marvell 9215 SATA controller (Bjorn Helgaas) * pci/virtualization: PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller PCI: Mark AMD Raven iGPU ATS as broken in some platforms
-
Bjorn Helgaas authored
- Save/restore Precision Time Measurement Capability for suspend/resume (David E. Box) - Disable PTM during suspend to save power (David E. Box) * pci/ptm: PCI: Disable PTM during suspend to save power PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
-
Bjorn Helgaas authored
- Add sysfs attribute for device power state (Maximilian Luz) - Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg) - Do not generate wakeup event when runtime resuming bus (Mika Westerberg) * pci/pm: PCI/PM: Do not generate wakeup event when runtime resuming device PCI/PM: Rename pci_wakeup_bus() to pci_resume_bus() PCI: Add sysfs attribute for device power state
-
Bjorn Helgaas authored
- Disable MSI for broken Pericom PCIe-USB adapter (Andy Shevchenko) - Move MSI/MSI-X init to msi.c (Bjorn Helgaas) - Move MSI/MSI-X flags updaters to msi.c (Bjorn Helgaas) - Warn if we assign 64-bit MSI address to device that only supports 32-bit MSI (Vidya Sagar) * pci/msi: PCI/MSI: Set device flag indicating only 32-bit MSI support PCI/MSI: Move MSI/MSI-X flags updaters to msi.c PCI/MSI: Move MSI/MSI-X init to msi.c PCI: Use predefined Pericom Vendor ID PCI: Disable MSI for Pericom PCIe-USB adapter
-
Bjorn Helgaas authored
- Update kernel-doc to match function prototypes (Mauro Carvalho Chehab) - Bounds-check "pci=resource_alignment=" requests (Bjorn Helgaas) - Fix integer overflow in "pci=resource_alignment=" requests (Colin Ian King) - Remove unused HAVE_PCI_SET_MWI definition (Heiner Kallweit) - Reduce pci_set_cacheline_size() message to debug level (Heiner Kallweit) * pci/misc: PCI: Reduce pci_set_cacheline_size() message to debug level PCI: Remove unused HAVE_PCI_SET_MWI PCI: Fix overflow in command-line resource alignment requests PCI: Bounds-check command-line resource alignment requests PCI: Fix kernel-doc markup # Conflicts: # drivers/pci/pci-driver.c
-
Bjorn Helgaas authored
- Remove unneeded break in ibmphp (Bjorn Helgaas) - Fix pci_slot_release() NULL pointer dereference (Jubin Zhong) * pci/hotplug: PCI: Fix pci_slot_release() NULL pointer dereference PCI: ibmphp: Remove unneeded break
-
Bjorn Helgaas authored
- Stop writing AER Capability when we don't own it (Sean V Kelley) - Bind RCEC devices to the Port driver (Qiuxu Zhuo) - Cache the RCEC RA Capability offset (Sean V Kelley) - Add pci_walk_bridge() (Sean V Kelley) - Clear AER status only when we control AER (Sean V Kelley) - Recover from RCEC AER errors (Sean V Kelley) - Add pcie_link_rcec() to associate RCiEPs with RCECs (Sean V Kelley) - Recover from RCiEP AER errors (Sean V Kelley) - Add pcie_walk_rcec() for RCEC AER handling (Sean V Kelley) - Add pcie_walk_rcec() for RCEC PME handling (Sean V Kelley) - Add RCEC AER error injection support (Qiuxu Zhuo) * pci/err: PCI/AER: Add RCEC AER error injection support PCI/PME: Add pcie_walk_rcec() to RCEC PME handling PCI/AER: Add pcie_walk_rcec() to RCEC AER handling PCI/ERR: Recover from RCiEP AER errors PCI/ERR: Add pcie_link_rcec() to associate RCiEPs PCI/ERR: Recover from RCEC AER errors PCI/ERR: Clear AER status only when we control AER PCI/ERR: Add pci_walk_bridge() to pcie_do_recovery() PCI/ERR: Avoid negated conditional for clarity PCI/ERR: Use "bridge" for clarity in pcie_do_recovery() PCI/ERR: Simplify by computing pci_pcie_type() once PCI/ERR: Simplify by using pci_upstream_bridge() PCI/ERR: Rename reset_link() to reset_subordinates() PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities() PCI/ERR: Bind RCEC devices to the Root Port driver PCI/AER: Write AER Capability only when we control it
-
Bjorn Helgaas authored
- Decode PCIe 64 GT/s link speed (Gustavo Pimentel) - De-duplicate Device IDs in the driver dynamic IDs list (Zhenzhong Duan) - Return u8 from pci_find_capability() and similar (Puranjay Mohan) - Return u16 from pci_find_ext_capability() and similar (Bjorn Helgaas) - Include both device and resource name in config space resources (Alexander Lobakin) - Fix ACPI companion lookup for device 0 on the root bus (Rafael J. Wysocki) * pci/enumeration: PCI/ACPI: Fix companion lookup for device 0 on the root bus PCI: Keep both device and resource name for config space remaps PCI: Return u16 from pci_find_ext_capability() and similar PCI: Return u8 from pci_find_capability() and similar PCI: Avoid duplicate IDs in driver dynamic IDs list PCI: Move pci_match_device() ahead of new_id_store() PCI: Decode PCIe 64 GT/s link speed
-
Bjorn Helgaas authored
- Save/restore ASPM L1SS Capability for suspend/resume (Vidya Sagar) * pci/aspm: PCI/ASPM: Save/restore L1SS Capability for suspend/resume
-
Bjorn Helgaas authored
Add function 1 DMA alias quirk for Marvell 88SS9215 PCIe SSD Controller. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 Link: https://lore.kernel.org/r/20201110220516.697934-1-helgaas@kernel.org Reported-by:
John Smith <LK7S2ED64JHGLKj75shg9klejHWG49h5hk@protonmail.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
- Dec 12, 2020
-
-
Rafael J. Wysocki authored
In some cases acpi_pci_find_companion() returns an incorrect device object as the ACPI companion for device 0 on the root bus (bus 0). On the affected systems that device is the PCI interface to the host bridge and the "ACPI companion" returned for it corresponds to a non-PCI device located in the SoC (e.g. a sensor on an I2C bus). As a result of this, the ACPI device object "attached" to PCI device 00:00.0 cannot be used for enumerating the device that is really represented by it which (of course) is problematic. Address that issue by preventing acpi_pci_find_companion() from returning a device object with a valid _HID (which by the spec should not be present uder ACPI device objects corresponding to PCI devices) for PCI device 00:00.0. [bhelgaas: use pci_is_root_bus()] Link: https://lore.kernel.org/linux-acpi/1409ba0c-1580-dc09-e6fe-a0c9bcda6462@gmail.com/ Link: https://lore.kernel.org/r/4673285.9aE2nYKHPr@kreacher Reported-by:
Daniel Scally <djrscally@gmail.com> Tested-by:
Daniel Scally <djrscally@gmail.com> Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Daniel Scally <djrscally@gmail.com>
-
- Dec 11, 2020
-
-
Alexander Lobakin authored
Follow the rule taken in commit 35bd8c07 ("devres: keep both device name and resource name in pretty name") and keep both device and resource names while requesting memory regions for PCI config space to prettify e.g. /proc/iomem output: Before (DWC Host Controller): 18b00000-18b01fff : dbi 18b10000-18b11fff : config 18b20000-18b21fff : dbi 18b30000-18b31fff : config After: 18b00000-18b01fff : 18b00000.pci dbi 18b10000-18b11fff : 18b00000.pci config 18b20000-18b21fff : 18b20000.pci dbi 18b30000-18b31fff : 18b20000.pci config Link: https://lore.kernel.org/r/WbKfdybjZ6xNIUjcC5oC8NcuLqrJfkxQAlnO80ag@cp3-web-020.plabs.ch Signed-off-by:
Alexander Lobakin <alobakin@pm.me> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Krzysztof Wilczyński authored
Removed unused ".bus_shift" initialisers from pci-xgene.c as xgene_pcie_map_bus() did not use these. Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20201129230743.3006978-6-kw@linux.com Signed-off-by:
Krzysztof Wilczyński <kw@linux.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Krzysztof Wilczyński authored
Use "void __iomem" instead "char __iomem" pointer type when working with the accessor functions (with names like readb() or writel(), etc.) to better match a given accessor function signature where commonly the address pointing to an I/O memory region would be a "void __iomem" pointer. Related: https://lwn.net/Articles/102232/ Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20201129230743.3006978-5-kw@linux.com Signed-off-by:
Krzysztof Wilczyński <kw@linux.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Jon Derrick <jonathan.derrick@intel.com>
-
Krzysztof Wilczyński authored
Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be used instead. Use the ALIGN_DOWN() macro to ensure that PCI Express ECAM offset is always 32 bit aligned. Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20201129230743.3006978-4-kw@linux.com Signed-off-by:
Krzysztof Wilczyński <kw@linux.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Krzysztof Wilczyński authored
Add a custom constant for the ".bus_shift" initialiser to capture a non-standard platform-specific ECAM bus shift value. Standard values otherwise defined in the PCI Express Specification are available in the include/linux/pci-ecam.h. Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20201129230743.3006978-3-kw@linux.com Signed-off-by:
Krzysztof Wilczyński <kw@linux.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Krzysztof Wilczyński authored
Add ECAM-related constants to provide a set of standard constants defining memory address shift values to the byte-level address that can be used to access the PCI Express Configuration Space, and then move native PCI Express controller drivers to use the newly introduced definitions retiring driver-specific ones. Refactor pci_ecam_map_bus() function to use newly added constants so that limits to the bus, device function and offset (now limited to 4K as per the specification) are in place to prevent the defective or malicious caller from supplying incorrect configuration offset and thus targeting the wrong device when accessing extended configuration space. This refactor also allows for the ".bus_shift" initialisers to be dropped when the user is not using a custom value as a default value will be used as per the PCI Express Specification. Thanks to Qian Cai <qcai@redhat.com>, Michael Walle <michael@walle.cc>, and Vladimir Oltean <olteanv@gmail.com> for reporting a pci_ecam_create() issue with .bus_shift and to Vladimir for proposing the fix. [bhelgaas: incorporate Vladimir's fix, update commit log] Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20201129230743.3006978-2-kw@linux.com Tested-by:
Michael Walle <michael@walle.cc> Signed-off-by:
Krzysztof Wilczyński <kw@linux.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Jon Derrick <jonathan.derrick@intel.com> Reviewed-by:
Bjorn Helgaas <bhelgaas@google.com>
-
David E. Box authored
There are systems (for example, Intel based mobile platforms since Coffee Lake) where the power drawn while suspended can be significantly reduced by disabling Precision Time Measurement (PTM) on PCIe root ports as this allows the port to enter a lower-power PM state and the SoC to reach a lower-power idle state. To save this power, disable the PTM feature on root ports during pci_prepare_to_sleep() and pci_finish_runtime_suspend(). The feature will be returned to its previous state during restore and error recovery. Suggested-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=209361 Link: https://lore.kernel.org/r/20201207223951.19667-2-david.e.box@linux.intel.com Reported-by:
Len Brown <len.brown@intel.com> Signed-off-by:
David E. Box <david.e.box@linux.intel.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
David E. Box authored
The PCI subsystem does not currently save and restore the configuration space for the Precision Time Measurement (PTM) Extended Capability leading to the possibility of the feature returning disabled on S3 resume. This has been observed on Intel Coffee Lake desktops. Add save/restore of the PTM control register. This saves the PTM Enable, Root Select, and Effective Granularity bits. Suggested-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/20201207223951.19667-1-david.e.box@linux.intel.com Signed-off-by:
David E. Box <david.e.box@linux.intel.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Alex Deucher authored
Edgar reported [1] AMD Raven iGPU errors on several of his systems. There is no root cause. Turn off ATS on these systems to avoid the issue. [1] https://lore.kernel.org/linux-iommu/MWHPR10MB1310CDB6829DDCF5EA84A14689150@MWHPR10MB1310.namprd10.prod.outlook.com/ [bhelgaas: commit log] Link: https://lore.kernel.org/r/MWHPR10MB131082779A86BE4CCCF190B789CB0@MWHPR10MB1310.namprd10.prod.outlook.com Reported-by:
Edgar Merger <Edgar.Merger@emerson.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
- Dec 10, 2020
-
-
Kishon Vijay Abraham I authored
Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl" phandle. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl" phandle. If the offset is not provided in "ti,syscon-pcie-ctrl", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20201210124917.24185-5-kishon@ti.com Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org>
-
Kishon Vijay Abraham I authored
Add PCIe EP mode dt-bindings for TI's J7200 SoC. Link: https://lore.kernel.org/r/20201210124917.24185-4-kishon@ti.com Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org>
-
Kishon Vijay Abraham I authored
Add host mode dt-bindings for TI's J7200 SoC. Link: https://lore.kernel.org/r/20201210124917.24185-3-kishon@ti.com Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org>
-
Kishon Vijay Abraham I authored
Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with argument. The argument is the register offset within "syscon" used to configure PCIe controller. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20201210124917.24185-2-kishon@ti.com Fixes: 431b53b8 ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC") Fixes: 45b39e92 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC") Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org>
-
Vidya Sagar authored
Set DMA mask to 32-bit while allocating the MSI target address so that the address is usable for both 32-bit and 64-bit MSI capable devices. Throw a warning if it fails to set the mask to 32-bit to alert that devices that are only 32-bit MSI capable may not work properly. Link: https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com Signed-off-by:
Vidya Sagar <vidyas@nvidia.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Robin Murphy <robin.murphy@arm.com>
-
- Dec 09, 2020
-
-
Manivannan Sadhasivam authored
For SM8250, we need to write the BDF to SID mapping in PCIe controller register space for proper working. This is accomplished by extracting the BDF and SID values from "iommu-map" property in DT and writing those in the register address calculated from the hash value of BDF. In case of collisions, the index of the next entry will also be written. For the sake of it, let's introduce a "config_sid" callback and do it conditionally for SM8250. Link: https://lore.kernel.org/r/20201208121402.178011-4-mani@kernel.org Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
-
Heiner Kallweit authored
Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying message like the following that results in user questions whether something is broken: xhci_hcd 0000:00:15.0: cache line size of 64 is not supported Root cause of the message is that on several chips the Cache Line Size register is hard-wired to 0. Change this message to debug level; an interested caller can still inform the user (if deemed helpful) based on the return code. Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
Heiner Kallweit authored
Remove unused HAVE_PCI_SET_MWI. Link: https://lore.kernel.org/r/03f20cac-708d-7897-c7c7-cb4e63cfd991@gmail.com Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
-
- Dec 08, 2020
-
-
Manivannan Sadhasivam authored
The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of ops_2_7_0. The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid callback, which will be added in successive commit. Link: https://lore.kernel.org/r/20201208121402.178011-3-mani@kernel.org Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
-
Manivannan Sadhasivam authored
Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region. Link: https://lore.kernel.org/r/20201208121402.178011-2-mani@kernel.org Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
Rob Herring <robh@kernel.org>
-