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Commit 106d4ffd authored by Aditya Swarup's avatar Aditya Swarup Committed by Manasi Navare
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drm/i915/tgl: Add definitions for VRR registers and bits



Add definitions for registers grouped under Transcoder VRR function
with necessary bitfields.

Bspec: 49268

v2: Use REG_GENMASK, correct tabs/space indentation and move the
definitions near the transcoder section.(Jani)

v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)

v4: Use 'trans' in macro for better readability.(Manasi)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarAditya Swarup <aditya.swarup@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200319015941.28008-1-aditya.swarup@intel.com
parent 35f3fd81
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