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Commit fced4dde authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Quanyang Wang
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clk: zynqmp: pll: Remove the limit

commit 9ea2a0096156b687061931f9016027996d54b559 from
https://github.com/Xilinx/linux-xlnx.git

 xlnx_rebase_v6.1

The range is taken care in the zynqmp_pll_round_rate. Remove the rate range
in the zynqmp_clk_register_pll() to prevent the early truncation of the
frequencies and also allow multiple combinations of child and parent to get
more accurate rates. There are many changes since 5.15 specifically commit
c80ac50c ("clk: Always set the rate on clk_set_range_rate") that
changed the behavior of the clock framework. So the issue is not observed
in the earlier release.

Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
State: pending
Signed-off-by: default avatarQuanyang Wang <quanyang.wang@windriver.com>
parent 02d9803e
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