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Commit fab38333 authored by Thinh Nguyen's avatar Thinh Nguyen Committed by Felipe Balbi
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usb: dwc3: Add SoftReset PHY synchonization delay 



From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: default avatarThinh Nguyen <thinhn@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent cabdf83d
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