drivers: clk: zynqmp: update divider round rate logic

commit bcd668f965ee8c36247b9e0c5f1cfb3e6534f3ab from
https://github.com/Xilinx/linux-xlnx.git

 xlnx_rebase_v6.1

Currently zynqmp divider round rate is considering single parent and
calculating rate and parent rate accordingly. But if divider clock flag
is set to SET_RATE_PARENT then its not trying to traverse through all
parent rate and not selecting best parent rate from that. So use common
divider_round_rate() which is traversing through all clock parents and
its rate and calculating proper parent rate.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
State: pending
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>