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Commit eb662f85 authored by Maxime Ripard's avatar Maxime Ripard
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clk: sunxi: pll2: Add A13 support



The A13, unlike the A10 and A20, doesn't use a pass-through exception for
the 0 value in the pre and post dividers, but increments all the values
written in the register by one.

Add an exception for both these cases to handle them nicely.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 460d0d44
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