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Unverified Commit e3f4e5b1 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
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ASoC: fsl_sai: Configure dataline/FIFO information from dts property



The SAI has multiple successive FIFO registers, but in some use
case the required dataline/FIFOs are not successive, so need
get such information from dts property "fsl,dataline"

fsl,dataline has 3 values for each configuration:
first one means the type: I2S(1) or DSD(2),
second one is dataline mask for 'rx',
third one is dataline mask for 'tx'.

Also set dma peripheral address and TRCE bits according to data lane.

Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: default avatarViorel Suman <viorel.suman@nxp.com>
Link: https://lore.kernel.org/r/1655451877-16382-8-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6b878ac2
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