spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

commit 9f520f054cb28c9633b5c0707e0bc155a8cc0b99 from
https://github.com/linux4microchip/linux.git linux-6.6-mchp+fpga

While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.

Fixes: 9ac8d176

 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Steve Wilkins <steve.wilkins@raymarine.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: harish h <harish.h@windriver.com>