mmc: sdhci-of-aspeed: Configure the SDHCIs as specified by the devicetree.
The hardware provides capability configuration registers for each SDHCI in the global configuration space for the SD controller. Writes to the global capability registers are mirrored to the capability registers in the associated SDHCI. Configuration of the capabilities must be written through the mirror registers prior to initialisation of the SDHCI. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210524073308.9328-5-steven_lee@aspeedtech.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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