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Commit dc32c1db authored by Rajan Vaja's avatar Rajan Vaja Committed by Quanyang Wang
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clk: zynqmp: Sync with mainline

commit  26e3a6655a00e9cd02d5d35f62e90ce14aa3a206 from
https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.10

While upstreaming some changes have been made based on reviews.
This patch is syncing up them by reverting internal patches:
commit 3100e267337d ("clk: zynqmp: Map ZYNQMP_CLK_SET_RATE_GATE with CCF"),
commit dee65b65916d ("clk: zynqmp: Use firmware specific mux clock flags"),
commit a3cfc9e40b81 ("clk: zynqmp: Use firmware specific divider clock
flags"), commit 54ed8a78f1d1 ("clk: zynqmp: Use firmware specific common
clock flags"), commit 0851d74ff743 ("clk: zynqmp: Handle divider specific
read only flag")

by upstream versions:
commit 03aea91b ("clk: zynqmp: Handle divider specific read only
flag"), commit 54530ed1 ("clk: zynqmp: Use firmware specific mux clock
flags"), commit 1b09c308 ("clk: zynqmp: Use firmware specific divider
clock flags"), commit 610a5d83

 ("clk: zynqmp: Use firmware specific
common clock flags").

Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
State: pending
Signed-off-by: default avatarQuanyang Wang <quanyang.wang@windriver.com>
parent 6dea6cd7
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