octeontx2-af: fix 50G ethtool mapping

commit f1400dce652fc46ff4f4fd350ffad88f6183f063 from
git@git.assembla.com:cavium/WindRiver.linux.git

On Octeontx2 silicon 50G links are mapped with two serdes lanes
and Octeontx3 silicon they are mapped with single serdes lane.

This patch updates the ethtool link mode values against cgx modes
accordingly. A Separate patch will be pushed to rename CGX_MODE enum.

Change-Id: Ieb1ecf84ebed218fb012755110729403dfbe8828
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/57001


Reviewed-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Tested-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>