PCI: octeontx-83: add new quirks

commit 8ee3cf6f4a30a5d94755d8e38699b66245d08677 from
git@git.assembla.com:cavium/WindRiver.linux.git

1. OcteonTx needs Multibyte atomic I/O (LDST) for some devices.
LDST needs LMTLINE and LMTCANCEL to be mapped along with devices,
to be usable by software. Unfortunately devices like PKO and SSO
don't adevertize it in their BAR's. Adding a quirks to adds LMT
region in to PKO and SSOW at VBAR 2.

2. OcteonTx 83XX has SRIOV for PKO, SSO, FPA etc, most of them
dont have a Mailbox to communicate. Octeontx-83 desgin depends
on SSO mailbox.
The mailbox provided by SSO is 64 bits in each direction, which
is not sufficient for this, the latencies to do a trivial task is
very high. Solution is to hava a RAM based mailbox, this quirk adds
a VF BAR to SSOW with 64K RAM so that VF and PF can use this to
send messages. The desgin still uses SSO Mailbox for identity and
sending interrupts/notifications when message is pending.

3. octeontx-83xx has no FLR support and reset of blocks are required
in case of abrupt kill of application. This quirk disable bus reset
and do device reset though octeontx.

Change-Id: Ideece988711f774b6cf1d73416c40f1f1c5b105e
Signed-off-by: Harman Kalra <hkalra@marvell.com>
[RQ: change function reset_cavium_octeon_vf() type to fix build issue.]
Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>