Skip to content
Commit be5b5fcb authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries 



Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a9391e01
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment