coresight: tmc: Fixes for Marvell OcteonTx CN9xxx ETR HW issues.

commit 23a0e5dde140f37c47db1c5a31f2569524c19769 from
git@git.assembla.com:cavium/WindRiver.linux.git

1. For each HW issue, corresponding driver option will be enabled
   as listed below.

- Buffer size multiplier used is 8 byte instead of 4 bytes
  Driver option CORESIGHT_OPTS_BUFFSIZE_8BX handles this.

- Non secure trace buffer not supported
  Driver option CORESIGHT_OPTS_SECURE_BUFF handles this.
  Driver uses SMC calls for managing secure trace buffer.

- Control registers not reset upon cpu reset
  Driver option CORESIGHT_OPTS_RESET_CTL_REG handles this.

2. SMC call for secure buffer allocation do have the option of
   requesting LLC locked buffer. This can be enabled using
   "cache-lock" property in the DTS.

3. We do make an assumption that secure trace buffer is equally partitioned
   among all the cpus. This will keep the buffer allocation simplified
   in secure world. Hence we expect, arm-buffer-size DTS attribute value
   be same for all the ETR nodes.

Change-Id: I4a6acaf0dc38fb48c27204674458e173e25f83c0
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/16636


[Kevin: Adjust the code according to the changes made by commit
75f4e361]
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>