v4l: xilinx: dma: Fix back pressure on upstream entities in LLP2

commit 65fec623099ddab775616ef311ecab468cbc978b from
https://github.com/Xilinx/linux-xlnx.git

 xlnx_rebase_v5.15

In LLP2 (Xilinx low latency with SyncIP) case, the pipeline is started
before the dmaengine. This will cause back pressure on upstream entities.
This was not visible with SDI/HDMI Rx pipeline but only with
MIPI CSI2 Rx as it can't handle back pressure.

This is modified by starting the pipeline in V4L2_CID_XILINX_LOW_LATENCY
control, called with XVIP_START_DMA, after VIDIOC_STREAMON has been called.

Signed-off-by: Anil Mamidala <anil.mamidala@amd.com>
Signed-off-by: Sunil Vaghela <sunil.vaghela@amd.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
State: pending
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>