PCI: j721e: Add PCI legacy interrupt support for J7200

commit 0cc7dd00c998242b68e5ffe1d630f2198a4385db from
git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git



Add PCI legacy interrupt support for J7200. J7200 has a single HW
interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in J7200 has provided USER_EOI_REG register. When the SW writes to
USER_EOI_REG register after handling the interrupt, the IP checks the
state of legacy interrupt and re-triggers pulse interrupt invoking
the handler again. (Note that the errata in J721E where EOI is not
implemented is fixed in J7200).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/all/20210804132912.30685-4-kishon@ti.com/


Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Xulin Sun <xulin.sun@windriver.com>