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Commit a1304d35 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
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arm64: tegra: Enable DFLL clock on Jetson TX1 



Enable DFLL clock for Jetson TX1 platform.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a5e98b0b
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