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Commit 931da6a0 authored by Zhang Rui's avatar Zhang Rui Committed by Rafael J. Wysocki
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powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR



On Sapphire Rapids, the layout of the Psys domain Power Limit Register
is different from from what it was before.

Enhance the code to support the new Psys PL register layout.

Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Reported-and-tested-by: default avatarAlkattan Dana <dana.alkattan@intel.com>
[ rjw: Subject and changelog edits ]
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 2585cf9d
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