arm64: Use nops between LDs and STs

commit 1fd319eea1e4b1263f878455f2714f38932c0ef8 from
git@git.assembla.com:cavium/WindRiver.linux.git

An issue exists in T83xx chip where the CPU can
incorrectly forward data from an older store to a
younger load when addresses differ by bit 55.
When this happens L1 Dcache parity error occurs in
hardware and Synchronous parity error abort is raised
to software. Kernel and User virtual addresses always
differ by bit 55 and also load, store operations between
those VAs happen at __arch_copy_to/from_user only.
Hence as a workaround __arch_copy_to/from_user
functions are modified to use nops between loads and
stores for T83 CPU.

Change-Id: I5ff497cf927d1bd2f41e28d813da59f35022483d
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/26580


Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com>
Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com>
Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>