ARM: Enhance platform support for Intel Axxia AXM55xx

These changes are specific for the AXM55xx Intel AXXIA SoCs.
This covers all changes in the arch/arm/mach-axxia directory in order
to complete the initial support started with commit 1d22924e
("ARM: Add platform support for LSI AXM55xx SoC").

The AXM55xx family consists of devices that may contain up to 16 ARM
Cortex-A15 cores (in a 4x4 cluster configuration). The cores within
each cluster share an L2 cache, and the clusters are connected to each
other via a CCN-504 cache coherent interconnect

Signed-off-by: John Jacques <john.jacques@intel.com>
Signed-off-by: Anders Berg <anders.berg@intel.com>
Signed-off-by: Magnus Karlsson <magnus.karlsson@intel.com>
Signed-off-by: Gary McGee <gary.mcgee@intel.com>
Signed-off-by: SangeethaRao <sangeetha.rao@intel.com>
Signed-off-by: Palani <palaniappan.ramanathan@intel.com>
Signed-off-by: Charlie Paul <charlie.paul@windriver.com>
Signed-off-by: Daniel Dragomir <daniel.dragomir@windriver.com>