drivers: clk: zynqmp: add hack to use old algorithm for divider round rate
commit 2c41e2c9cb65dd4a6454488c2e37b8cbc85db6f0 from https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v6.1 Currently on ZynqMP platform, PL clocks are affecting because RPLL rate is changed run time by DP audio driver. Since RPLL is shared between DP audio clock and PL clocks it is affecting PL clocks. With old algorithm of zynqmp_clk_divider_round_rate(), RPLL rate change was minor and its affecting PL clocks less. E.g., changing RPLL rate from 1199.880 MHz to 1204.224 MHz which changes PL clock rate from 39.99 MHz to 40.1 MHz. While with new algorithm its selecting different RPLL frequency and divider value to get same frequency e.g., its changing RPLL rate from 1199.880 MHz to 761.855925 MHz and affecting PL clock more. But dprxss driver which is using PL clock should handle this rate change since RPLL is shared with DP clock and it must adjust to new rate runtime. So, as temporary solution, use old algorithm for Versal and ZynqMP platforms and remove this hack and use new algorithm once dprxss driver is handling clock rate change runtime. Signed-off-by:Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by:
Loading