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Commit 697624ee authored by Adam Ford's avatar Adam Ford Committed by Ulf Hansson
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pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain



According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of
hdmi rx verification IP that should not enable for HDMI TX.
But actually if the clock is disabled before HDMI/LCDIF probe,
LCDIF will not get pixel clock from HDMI PHY and print the error
logs:

[CRTC:39:crtc-2] vblank wait timed out
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260

Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewed-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarSandor Yu <Sandor.yu@nxp.com>
Link: https://lore.kernel.org/r/20240203165307.7806-5-aford173@gmail.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent a0691f28
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