ASoC: cs35l41: Correct handling of some registers in the cache
It makes no sense to cache the test/user key registers, since they require values written at specific times, mark them volatile. It is probably best if they can't be accessed from user-space either, so mark them precious as well. The interrupt force, edge, polarity and debounce are all settings applied to the IRQ rather than status bits and as such should not be volatile. The OTP trim values will require re-application in the event of a cache sync and as such should not be volatile. The OTPID however should be volatile. The DSP scratch registers are used to read back an error/debug code from the DSP on shutdown, as such these should be marked volatile. Finally, add some missing defaults, add TST_FS_MON0, and allow the DSP core control register to be cached. Signed-off-by:Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220105113026.18955-5-ckeepax@opensource.cirrus.com Signed-off-by:
Mark Brown <broonie@kernel.org>
parent
56852cf4
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