Skip to content
Commit 5d33481f authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g043: Add WDT clock and reset entries 



Add WDT{0,2} clock and reset entries to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6c05648b
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment