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Commit 564c836f authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT 

Commit 930beb5a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5a

 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent baf5cb30
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