net: macb: Set MDIO clock divisor for pclk higher than 160MHz

commit cc7310fda242b85900cc805b028f2f21d1d8f210 from
https://github.com/Xilinx/linux-xlnx.git

 xlnx_rebase_v6.1

Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
State: upstream (b31587fe)
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>