edac: Add Axxia Error Detection & Correction support

commit  d7a78a8c8943d543aa6ab068c9941b5de1cb452e from
https://github.com/axxia/linux-yocto.git

 axxia-linux/v5.10/standard/axxia-dev/base

Add Intel Axxia Error Detection & Correction [EDAC] cache L1/L2/L3,
SMEM and CMEM drivers for Axxia AXM55xx, X9/AXM56xx and XLF/AXC67xx.
Added linux style debug CMEM option.

Changes:
- CMEM/SMEM driver trace capabilities added
- CMEM/SMEM cpu0 affinity used
- SMEM code maintainability improved
- CMEM multiple ca parity error event added
- CMEM mpr dump on signal bit [21]
- CMEM clear mr5 ca parity error flag added
- CMEM irq storm fix
- fix issue with nca ring access
- added tracepoints for L3 cache
- changed from CMEM debug local define to Kconfig parameter

Signed-off-by: Marek Majtyka <marekx.majtyka@intel.com>
Signed-off-by: John Jacques <john.jacques@intel.com>
Signed-off-by: Charlie Paul <charlie.paul@windriver.com>
Signed-off-by: Daniel Dragomir <daniel.dragomir@windriver.com>
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
[Quanyang:
1. add "depends on ARCH_AXXIA" for EDAC_AXXIA_L3_5600/EDAC_AXXIA_L3_6700/EDAC_AXXIA_L2_CPU_5600/EDAC_AXXIA_L2_CPU_6700
to avoid them building for arm, this is to fix allyesconfig building error.
2. add "depends on MACH_AXXIA" for EDAC_AXXIA_L2_CPU_5500 to fix to
avoid them building from arm64, this is to fix allyesconfig building error.
3. change axxia_edac_cmem_proc_ops to proc_ops.
4. change header file "#include "axxia_l2_55xx.h"" to "#include <asm/axxia_l2_55xx.h>"in axxia_edac-l2_cpu.c.]