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Commit 43cd9175 authored by Maxime Ripard's avatar Maxime Ripard Committed by Meng Li
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drm/vc4: Increase the core clock based on HVS load

commit  7c3c743f2cb4f40698e3b54707860a863be510e2 from
https://github.com/raspberrypi/linux.git

 rpi-5.15.y

Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.

Failing to do so will result in a vblank timeout and a stalled display
pipeline.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Signed-off-by: default avatarMeng Li <Meng.Li@windriver.com>
parent 086b4409
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