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Commit 3e1531db authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
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clk: rockchip: fix the incorrect pclk_edp div width for RK3399 



The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: default avatarLin Huang <hl@rock-chips.com>
Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Tested-by: default avatarLin Huang <hl@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1a0abcd6
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