Skip to content
Commit 2ceed593 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

arm64: tegra: Add DFLL clock on Tegra210 



Add essential DFLL clock properties for Tegra210.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d428f35d
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment