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Commit 2bd9feed authored by Andrey Gusakov's avatar Andrey Gusakov Committed by Geert Uytterhoeven
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clk: renesas: r8a779[56]x: Add MLP clocks



Add clocks for MLP modules on Renesas R-Car H3 and M3-W/N SoCs.

Signed-off-by: default avatarAndrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: default avatarNikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20210929213431.5275-1-nikita.yoush@cogentembedded.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 373bd6f4
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