Skip to content
Commit 25bb2cec authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: sor: Factor out tegra_sor_set_parent_clock()



Switching the SOR parent clock can glitch if done while the clock is
enabled. Extract a common function that can be used to disable the
module clock, switch the parent and reenable the module clock.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 0751bb5c
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment