octeontx2-pcicons: adjust padding size for RT

commit 45969363f19fcede0a1029cecba7bf0748a3dc12 from
git@git.assembla.com:cavium/WindRiver.linux.git

Perform similar adjustments, although with greater precision, to what has
been done in commit 4b53a3418d84 ("octeontx2-pcicons: Adjust padding size
for RT").

The previous change only adjusted the offset of the `console_addr` field,
making sure it is on 128-byte offset in both RT and non-RT kernels.

Improve the previous adjustments by accounting for a fact, that if
CONFIG_PREEMPT_RT is set, spinlock_t grows by 44 bytes. That makes
the `in_use` field start at an unaligned offset. When kernel boots
and the driver tries to acquire the console, a data abort exception
is raised, crashing the system.

Fix this by adding 4 bytes padding when PREEMPT_RT is set and 48 bytes
if it is not set. That way every field after the spin lock object
stays at the same 64-bit aligned offset regardless we are running RT
or non-RT kernel, avoiding the data abort and making the whole struct
looks the same in both modes.

The fact that the structure is now unified in RT and non-RT modes makes
it easier to implement similar change in the console application and in
U-Boot PCI console driver. These two pieces of software must share the
same structure layout. Since they don't have the extended RT version of
the spin lock object, they can just have padding of the matching size.

Additionally, add build-time asserts making sure the fields after the
spin lock have the right offset.

Change-Id: I5b2f7ff73d4cc5ba329679d458f1071da0c17fe2
Signed-off-by: Wojciech Zmuda <wzmuda@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/86824


Reviewed-by: Rick Farrington <rfarrington@marvell.com>
Reviewed-by: Chandrakala Chavva <cchavva@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
[RQ: Adjust padding size to fix build issue.]
Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>