spi: spi-zynqmp-gqspi: Fix chipselect timeout issue

commit  beee98860eb0d93280cb6b8864891aadc7b345be from
https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.10

The existing implementation has a loophole where under a corner case the
driver may issue a transfer completion to the framework with data bytes
still present in the tx fifo.

The corner case is hit, when the controller gets into TXNOTFULL and
TXEMPTY conditions simultaneously while entering the ISR. This can happen
when TXNOTFULL condition has been met but there is significant delay in
entering the ISR (could be because Linux was busy processing some other
ISR). If the delay is long enough to drain out the remaining bytes in
txfifo, the interrupt status read in the ISR will show that both TXNOTFULL
and TXEMPTY conditions are hit. Along with these, if there is this
condition where the remaining bytes to be txed (and loaded into the fifo)
are less than or equal to fifo threshold, the bug in existing
implementation will end up issuing a completion message to the framework
with tx bytes left in fifo.
The subsequent chip deselect from framework will then stop further
transfers with left out tx bytes in the tx fifo.

The proposed fix in this patch uses the TXEMPTY interrupt to ensure that
the txfifo is completely emptied out before the upper layers are informed
of the transfer completion.
The patch also makes other changes with regards to the tx path handling in
the ISR.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
State: pending
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>