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Commit 06f1b06d authored by Chaitanya Kumar Borah's avatar Chaitanya Kumar Borah Committed by Jani Nikula
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drm/i915/display: Add 480 MHz CDCLK steps for RPL-U



A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.

v2: (Matt)
    - Add missing clock steps
    - Correct reference clock typo

v3: - Revert to RPL-U subplatform (Jani)

v4: - Remove Bspec reference from code (Jani)

Bspec: 55409
Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com
parent 61b795a9
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