drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
commit c938aed8 upstream. [Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by:Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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b60efcaf
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