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Commit fed0509c authored by Wenyou Yang's avatar Wenyou Yang Committed by Tom Rini
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clk: at91: add PLLADIV driver 



As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: default avatarWenyou Yang <wenyou.yang@microchip.com>
parent cb0cb1b0
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