Skip to content
Commit ee8b1e29 authored by Gabor Juhos's avatar Gabor Juhos Committed by Tom Rini
Browse files

MIPS: mips32/cache.S: store cache line size in t8 register 



Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
parent c3259165
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment