Skip to content
Commit e4916e2c authored by Elaine Zhang's avatar Elaine Zhang Committed by Kever Yang
Browse files

clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent 



Optimize setting process.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
parent cdf21a86
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment