stm32mp1: psci: add synchronization with ROM code

Use SGI0 interruption  and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
  RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
  + TAMP_BACKUP_BRANCH_ADDRESS
  + TAMP_BACKUP_MAGIC_NUMBER
  when magic is not egual to
  BOOT_API_A7_CORE0_MAGIC_NUMBER

This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>