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Commit aefc0b7a authored by Jagan Teki's avatar Jagan Teki
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clk: sunxi: h3: Implement EPHY CLK and RESET



EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Acked-by: default avatarJoe Hershberger <joe.hershberger@ni.com>
parent 68620c96
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